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1 features ? high-density, high-performance, electrically-erasable complex programmable logic device ? 3.0 or 3.6v operating range ? 32 macrocells ? 5 product terms per macrocell, expandable up to 40 per macrocell ?44 pins ? 15 ns maximum pin-to-pin delay ? registered operation up to 77 mhz ? enhanced routing resources in-system programmability (isp) via jtag flexible logic macrocell ? d/t latch configurable flip-flops ? global and individual register control signals ? global and individual output enable ? programmable output slew rate ? programmable output open collector option ? maximum logic utilization by burying a register with a com output advanced power management features ? automatic 5 a standby for ?l? version ? pin-controlled 100 a standby mode ? programmable pin-keeper inputs and i/os ? reduced-power feature per macrocell available in commercial and industrial temperature ranges available in 44-lead plcc and tqfp advanced eeprom technology ? 100% tested ? completely reprogrammable ? 10,000 program/erase cycles ? 20-year data retention ? 2000v esd protection ? 200 ma latch-up immunity jtag boundary-scan testing to ieee std. 1149.1-1990 and 1149.1a-1993 supported pci-compliant security fuse feature enhanced features improved connectivity (additional feedback routing, alternate input routing) output enable product terms d latch mode combinatorial output with registered feedback within any macrocell three global clock pins itd (input transition detection) circuits on global clocks, inputs and i/o fast registered input from product term programmable ?pin-keeper? option v cc power-up reset option pull-up option on jtag pins tms and tdi advanced power management features ? edge-controlled power-down ?l? ? individual macrocell power option ? disable itd on global clocks, inputs and i/o high- performance eeprom cpld atf1502asv ATF1502ASVL rev. 1615b?05/00
atf1502asv(l) 2 44-lead tqfp top view 44-lead plcc top view description the atf1502asv is a high-performance, high-density complex programmable logic device (cpld) that utilizes atmel?s proven electrically-erasable technology. with 32 logic macrocells and up to 36 inputs, it easily integrates logic from several ttl, ssi, msi, lsi and classic plds. the atf1502asv?s enhanced routing switch matrices increase usable gate count and the odds of successful pin- locked design modifications. the atf1502asv has up to 32 bi-directional i/o pins and four dedicated input pins, depending on the type of device package selected. each dedicated pin can also serve as a global control signal, register clock, register reset or output enable. each of these control signals can be selected for use individually within each macrocell. 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 i/o/tdi i/o i/o gnd pd1/i/o i/o tms/i/o i/o vcc i/o i/o i/o i/o/tdo i/o i/o vcc i/o i/o i/o/tck i/o gnd i/o 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 i/o i/o i/o i/o gnd vcc i/o pd2/i/o i/o i/o i/o i/o i/o i/o vcc i/oe2/gck2 gclr/i i/oe1 gck1/i gnd gck3 i/o 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 tdi/i/o i/o i/o gnd pd1/i/o i/o i/o/tms i/o vcc i/o i/o i/o i/o/tdo i/o i/o vcc i/o i/o i/o/tck i/o gnd i/o 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 i/o i/o i/o i/o gnd vcc i/o pd2/i/o i/o i/o i/o i/o i/o i/o vcc gck2/oe2/i gclr/i oe1/i gck1/i gnd i/o/gclk3 i/o
atf1502asv(l) 3 block diagram each of the 32 macrocells generates a buried feedback that goes to the global bus. each input and i/o pin also feeds into the global bus. the switch matrix in each logic block then selects 40 individual signals from the global bus. each macrocell also generates a foldback logic term that- goes to a regional bus. cascade logic between macrocells in the atf1502asv allows fast, efficient generation of complex logic functions. the atf1502asv contains four such logic chains, each capable of creating sum term logic with a fan-in of up to 40 product terms. the atf1502asv macrocell, shown in figure 1, is flexible enough to support highly complex logic functions operating at high speed. the macrocell consists of five sections: product terms and product term select multiplexer, or/xor/cascade logic, a flip-flop, output select and enable, and logic array inputs. unused product terms are automatically disabled by the compiler to decrease power consumption. a security fuse, when programmed, protects the contents of the atf1502asv. two bytes (16 bits) of user signature are accessible to the user for purposes such as storing project name, part number, revision or date. the user signature is accessible regardless of the state of the security fuse. the atf1502asv device is an in-system programmable (isp) device. it uses the industry standard 4-pin jtag interface (ieee std. 1149.1), and is fully compliant with jtag?s boundary-scan description language (bsdl). isp allows the device to be programmed without removing it from the printed circuit board. in addition to simplifying the manufacturing flow, isp also allows design modifications to be made in the field via software. b 32
atf1502asv(l) 4 figure 1. atf1502asv macrocell product terms and select mux each atf1502asv macrocell has five product terms. each product term receives as its inputs all signals from both the global bus and regional bus. the product term select multiplexer (ptmux) allocates the five product terms as needed to the macrocell logic gates and control signals. the ptmux programming is deter- mined by the design compiler, which selects the optimum macrocell configuration. or/xor/cascade logic the atf1502asv ? s logic structure is designed to efficiently support all types of logic. within a single macrocell, all the product terms can be routed to the or gate, creating a 5-input and/or sum term. with the addition of the casin from neighboring macrocells, this can be expanded to as many as 40 product terms with little additional delay. the macrocell ? s xor gate allows efficient implementation of compare and arithmetic functions. one input to the xor comes from the or sum term. the other xor input can be a product term or a fixed high or low level. for combinato- rial outputs, the fixed level input allows polarity selection. for registered functions, the fixed levels allow demorgan minimization of product terms. the xor gate is also used to emulate t- and jk-type flip-flops. flip-flop the atf1502asv ? s flip-flop has very flexible data and con- trol functions. the data input can come from either the xor gate, from a separate product term or directly from the i/o pin. selecting the separate product term allows creation of a buried registered feedback within a combinatorial output macrocell. (this feature is automatically implemented by the fitter software). in addition to d, t, jk and sr opera- tion, the flip-flop can also be configured as a flow-through latch. in this mode, data passes through when the clock is high and is latched when the clock is low. the clock itself can be either one of the global clk signals (gck[0 : 2]) or an individual product term. the flip-flop changes state on the clock ? s rising edge. when the gck signal is used as the clock, one of the macrocell product terms can be selected as a clock enable. when the clock enable function is active and the enable signal (product term) is low, all clock edges are ignored. the flip-flop ? s asynchronous reset signal (ar) can be either the global clear (gclear), a product term, or always off. ar can also be a logic or of gclear with a product term. the asynchronous preset (ap) can be a product term or always off.
atf1502asv(l) 5 output select and enable the atf1502asv macrocell output can be selected as registered or combinatorial. the buried feedback signal can be either combinatorial or registered signal regardless of whether the output is combinatorial or registered. the output enable multiplexer (moe) controls the output enable signals. any buffer can be permanently enabled for simple output operation. buffers can also be permanently disabled to allow use of the pin as an input. in this configu- ration all the macrocell resources are still available, including the buried feedback, expander and cascade logic. the output enable for each macrocell can be selected as either of the two dedicated oe input pins, as an i/o pin configured as an input, or as an individual product term. global bus/switch matrix the global bus contains all input and i/o pin signals as well as the buried feedback signal from all 32 macrocells. the switch matrix in each logic block receives as its inputs all signals from the global bus. under software control, up to 40 of these signals can be selected as inputs to the logic block. foldback bus each macrocell also generates a foldback product term. this signal goes to the regional bus and is available to four macrocells. the foldback is an inverse polarity of one of the macrocell ? s product terms. the four foldback terms in each region allow generation of high fan-in sum terms (up to nine product terms) with little additional delay. programmable pin-keeper option for inputs and i/os the atf1502asv offers the option of programming all input and i/o pins so that pin-keeper circuits can be uti- lized. when any pin is driven high or low and then subsequently left floating, it will stay at that previous high or low level. this circuitry prevents unused input and i/o lines from floating to intermediate voltage levels, which causes unnecessary power consumption and system noise. the keeper circuits eliminate the need for external pull-up resis- tors and eliminate their dc power consumption. input diagram i/o diagram speed/power management the atf1502asv has several built-in speed and power management features. the atf1502asv contains circuitry that automatically puts the device into a low-power standby mode when no logic transitions are occurring. this not only reduces power consumption during inactive periods, but also provides proportional power savings for most applica- tions running at system speeds below 50 mhz. this feature may be selected as a design option. to further reduce power, each atf1502asv macrocell has a reduced-power bit feature. this feature allows individual macrocells to be configured for maximum power savings. this feature may be selected as a design option.
atf1502asv(l) 6 the atf1502asv also has an optional power-down mode. in this mode, current drops to below 15 ma. when the power-down option is selected, either pd1 or pd2 pins (or both) can be used to power down the part. the power- down option is selected in the design source file. when enabled, the device goes into power-down when either pd1 or pd2 is high. in the power-down mode, all internal logic signals are latched and held, as are any enabled outputs. all pin transitions are ignored until the pd pin is brought low. when the power-down feature is enabled, the pd1 or pd2 pin cannot be used as a logic input or output. how- ever, the pin ? s macrocell may still be used to generate buried foldback and cascade logic signals. all power-down ac characteristic parameters are com- puted from external input or i/o pins, with reduced-power bit turned on. for macrocells in reduced-power mode (reduced-power bit turned on), the reduced-power adder, t rpa , must be added to the ac parameters, which include the data paths t lad , t lac , t ic , t acl , t ach and t sexp . the atf1502asv macrocell also has an option whereby the power can be reduced on a per-macrocell basis. by enabling this power-down option, macrocells that are not used in an application can be turned down, thereby reduc- ing the overall power consumption of the device. each output also has individual slew rate control. this may be used to reduce system noise by slowing down outputs that do not need to operate at maximum speed. outputs default to slow switching, and may be specified as fast switching in the design file. design software support atf1502asv designs are supported by several third-party tools. automated fitters allow logic synthesis using a variety of high-level description languages and formats. power-up reset the atf1502asv has a power-up reset option at two dif- ferent voltage trip levels when the device is being powered down. within the fitter, or during a conversion, if the ? power-reset ? option is turned ? on ? (the default option), the trip levels during power-up or power-down are at 2.8v. the user can change this default option from ? on ? to ? off ? (within the fitter or specify it as a switch during conversion). when this is done, the voltage trip level during power-down changes from 2.8v to 0.7v. this is to ensure a robust oper- ating environment. the registers in the atf1502asv are designed to reset during power-up. at a point delayed slightly from v cc cross- ing v rst , all registers will be reset to the low state. the output state will depend on the polarity of the buffer. this feature is critical for state machine initialization. how- ever, due to the asynchronous nature of reset and the uncertainty of how v cc actually rises in the system, the fol- lowing conditions are required: 1. the v cc rise must be monotonic, 2. after reset occurs, all input and feedback setup times must be met before driving the clock pin high, and 3. the clock must remain stable during t d . security fuse usage a single fuse is provided to prevent unauthorized copying of the atf1502asv fuse patterns. once programmed, fuse verify is inhibited. however, the 16-bit user signature remains accessible. programming atf1502asv devices are in-system programmable (isp) devices utilizing the 4-pin jtag protocol. this capability eliminates package handling normally required for pro- gramming and facilitates rapid design iterations and field changes. atmel provides isp hardware and software to allow pro- gramming of the atf1502asv via the pc. isp is performed by using either a download cable, a comparable board tester or a simple microprocessor interface. when using the isp hardware or software to program the atf1502asv devices, four i/o pins must be reserved for the jtag interface. however, the logic features that the macrocells have associated with these i/o pins are still available to the design for burned logic functions. to facilitate isp programming by the automated test equipment (ate) vendors. serial vector format (svf) files can be created by atmel-provided software utilities. atf1502asv devices can also be programmed using stan- dard third-party programmers. with a third-party programmer, the jtag isp port can be disabled, thereby allowing four additional i/o pins to be used for logic. contact your local atmel representatives or atmel pld applications for details.
atf1502asv(l) 7 isp programming protection the atf1502asv has a special feature that locks the device and prevents the inputs and i/o from driving if the programming process is interrupted for any reason. the inputs and i/o default to high-z state during such a con- dition. in addition, the pin-keeper option preserves the previous state of the input and i/o pms during programming. all atf1502asv devices are initially shipped in the erased state, thereby making them ready to use for isp. note: for more information refer to the ? designing for in-system programmability with atmel cplds ? application note. jtag-bst/isp overview the jtag boundary-scan testing is controlled by the test access port (tap) controller in the atf1502asv. the boundary-scan technique involves the inclusion of a shift- register stage (contained in a boundary-scan cell) adjacent to each component so that signals at component bound- aries can be controlled and observed using scan testing methods. each input pin and i/o pin has its own boundary- scan cell (bsc) to support boundary-scan testing. the atf1502asv does not include a test reset (trst) input pin because the tap controller is automatically reset at power-up. the five jtag modes supported include: sample/preload, extest, bypass, idcode and highz. the atf1502asv ? s isp can be fully described using jtag ? s bsdl as described in ieee standard 1149.1b. this allows atf1502asv programming to be described and implemented using any one of the third- party development tools supporting this standard. the atf1502asv has the option of using four jtag- standard i/o pins for boundary-scan testing (bst) and in-system programming (isp) purposes. the atf1502asv is programmable through the four jtag pins using the ieee standard jtag programming protocol established by ieee standard 1149.1 using 5v ttl-level programming signals from the isp interface for in-system programming. the jtag feature is a programmable option. if jtag (bst or isp) is not needed, then the four jtag control pins are available as i/o pins. jtag boundary-scan cell (bsc) testing the atf1502asv contains up to 32 i/o pins and four input pins, depending on the device type and package type selected. each input pin and i/o pin has its own boundary- scan cell (bsc) in order to support boundary-scan testing as described in detail by ieee standard 1149.1. a typical bsc consists of three capture registers or scan registers and up to two update registers. there are two types of bscs, one for input or i/o pin, and one for the macrocells. the bscs in the device are chained together through the capture registers. input to the capture register chain is fed in from the tdi pin while the output is directed to the tdo pin. capture registers are used to capture active device data signals, to shift data in and out of the device and to load data into the update registers. control signals are gen- erated internally by the jtag tap controller. the bsc configuration for the input and i/o pins and macrocells is shown below. bsc configuration for input and i/o pins (except jtag tap pins) note: the atf1502asv has a pull-up option on tms and tdi pins. this feature is selected as a design option.
atf1502asv(l) 8 notes: 1. not more than one output at a time should be shorted. duration of short circuit test should not exceed 30 sec. 2. i cc3 refers to the current in the reduced-power mode when macrocell reduced-power is turned on. note: typical values for nominal supply voltage. this parameter is only sampled and is not 100% tested. the ogi pin (high-voltage pin during programming) has a maximum capacitance of 12 pf. dc and ac operating conditions commercial industrial operating temperature (ambient) 0 c - 70 c-40 c - 85 c v cc (3.3v) power supply 3.0v = 3.6% 3.0v = 3.6% dc characteristics symbol parameter condition min typ max units i il input or i/o low leakage current v in = v cc -2 -10 a i ih input or i/o high leakage current 210 i oz tri-state output off-state current v o = v cc or gnd -40 40 a i cc1 power supply current, standby v cc = max v in = 0, v cc std mode com. 40 ma ind. 45 ma ? l ? mode com. 5 a ind. 5 a i cc2 power supply current, power-down mode v cc = max v in = 0, v cc ? pd ? mode 0.1 5.0 ma i cc3 (2) reduced-power mode supply current, standby v cc = max v in = 0, v cc std mode com. 25 ma ind. 30 ma v il input low voltage -0.3 0.8 v v ih input high voltage 2.0 v ccint + 0.3 v v ol output low voltage (ttl) v in = v ih or v il v cc = min, i ol = 8 ma com. 0.45 v ind. 0.45 output low voltage (cmos) v in = v ih or v il v cc = min, i ol = 0.1 ma com. 0.2 v ind. 0.2 v v oh output high voltage (ttl) v in = v ih or v il v cc = min, i oh = 2.0 ma 2.4 v output high voltage (cmos) v in = v ih or v il v ccio = min, i oh = -0.1 ma v ccio - 0.2 pin capacitance typ max units conditions c in 810pf v in = 0v; f = 1.0 mhz c i/o 810pf v out = 0v; f = 1.0 mhz
atf1502asv(l) 9 absolute maximum ratings* temperature under bias.................................. -40 c to +85 c *notice: stresses beyond those listed under ? absolute maximum ratings ? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: 1. minimum voltage is -0.6v dc, which may under- shoot to -2.0v for pulses of less than 20 ns. maximum output pin voltage is v cc + 0.75v dc, which may overshoot to 7.0v for pulses of less than 20 ns. storage temperature ..................................... -65 c to +150 c voltage on any pin with respect to ground .........................................-2.0v to +7.0v (1) voltage on input pins with respect to ground during programming.....................................-2.0v to +14.0v (1) programming voltage with respect to ground .......................................-2.0v to +14.0v (1) ac characteristics symbol parameter -15 -25 units minmaxminmax t pd1 input or feedback to non-registered output 3 15 25 ns t pd2 i/o input or feedback to non-registered feedback 312 25ns t su global clock setup time 11 20 ns t h global clock hold time 0 0 ns t fsu global clock setup time of fast input 3 5 ns t fh global clock hold time of fast input 1 2 mhz t cop global clock to output delay 8 13 ns t ch global clock high time 5 7 ns t cl global clock low time 5 7 ns t asu array clock setup time 4 5 ns t ah array clock hold time 4 6 ns t acop array clock output delay 15 25 ns t ach array clock high time 6 10 ns t acl array clock low time 6 10 ns t cnt minimum clock global period 13 22 ns f cnt maximum internal global clock frequency 76.9 50 mhz t acnt minimum array clock period 13 22 ns f acnt maximum internal array clock frequency 76.9 50 mhz f max maximum clock frequency 100 60 mhz t in input pad and buffer delay 2 2 ns
atf1502asv(l) 10 note: see ordering information for valid part numbers. timing model t io i/o input pad and buffer delay 2 2 ns t fin fast input delay 2 2 ns t sexp foldback term delay 8 12 ns t pexp cascade logic delay 1 1.2 ns t lad logic array delay 6 8 ns t lac logic control delay 6 8 ns t ioe internal output enable delay 3 4 ns t od1 output buffer and pad delay (slow slew rate = off; v cc = 3.3v; c l = 35 pf) 57ns ac characteristics (continued) symbol parameter -15 -25 units minmaxminmax
atf1502asv(l) 11 notes: 1. see ordering information for valid part numbers. 2. the t rpa parameter must be added to the t lad , t lac ,t tic , t acl , and t sexp parameters for macrocells running in the reduced- power mode. input test waveforms and measurement levels t r , t f = 1.5 ns typical output ac test loads ac characteristics (continued) symbol parameter -15 -25 units min max min max t zx1 output buffer enable delay (slow slew rate = off; v ccio = 5.0v; c l = 35 pf) 79ns t zx2 output buffer enable delay (slow slew rate = off; v ccio = 3.3v; c l = 35 pf) 79ns t zx3 output buffer enable delay (slow slew rate = on; v ccio = 5.0v/3.3v; c l = 35 pf) 10 11 ns t xz output buffer disable delay (c l = 5 pf) 6 7 ns t su register setup time 4 5 ns t h register hold time 4 5 ns t fsu register setup time of fast input 2 2 ns t fh register hold time of fast input 2 2 ns t rd register delay 1 2 ns t comb combinatorial delay 1 2 ns t ic array clock delay 6 7 ns t en register enable time 6 7 ns t glob global control delay 1 1 ns t pre register preset time 4 5 ns t clr register clear time 4 5 ns t uim switch matrix delay 2 2 ns t rpa reduced-power adder (2) 13 14 ns
atf1502asv(l) 12 power-down mode the atf1502asv includes an optional pin-controlled power-down feature. when this mode is enabled, the pd pin acts as the power-down pin. when the pd pin is high, the device supply current is reduced to less than 3 ma. during power-down, all output data and internal logic states are latched and held. therefore, all registered and combi- natorial output data remain valid. any outputs that were in a high-z state at the onset will remain at high-z. during power-down, all input signals except the power-down pin are blocked. input and i/o hold latches remain active to ensure that pins do not float to indeterminate levels, further reducing system power. the power-down pin feature is enabled in the logic design file. designs using the power- down pin may not use the pd pin logic array input. how- ever, all other pd pin macrocell resources may still be used, including the buried feedback and foldback product term array inputs. notes: 1. for slow slew outputs, add t sso . 2. pin or product term. power-down ac characteristics (1)(2) symbol parameter -15 -25 units min max min max t ivdh valid i, i/o before pd high 15 25 ns t gvdh valid oe (2) before pd high 15 25 ns t cvdh valid clock (2) before pd high 15 25 ns t dhix i, i/o don ? t care after pd high 25 35 ns t dhgx oe (2) don ? t care after pd high 25 35 ns t dhcx clock (2) don ? t care after pd high 25 35 ns t dliv pd low to valid i, i/o 1 1 s t dlgv pd low to valid oe (pin or term) 1 1 s t dlcv pd low to valid clock (pin or term) 1 1 s t dlov pd low to valid output 1 1 s
atf1502asv(l) 13 bsc configuration for mac 0 1 dq 0 1 0 1 dq dq capture dr capture dr update dr 0 1 0 1 dq dq tdi tdi outj oej shift shift clock clock mode tdo tdo bsc for dedicated input bsc for i/o pins and macrocells 0 1 d q tdi clock tdo pin pin
atf1502asv(l) 14 oe (1, 2) global oe pins gclr global clear pin gclk (1, 2, 3) global clock pins pd (1, 2) power-down pins tdi, tms, tck, tdo jtag pins used for boundary-scan testing or in-system programming gnd ground pins v cci vcc pins for the device (+3.3v) atf1502asv dedicated pinouts dedicated pin 44-lead tqfp 44-lead j-lead input/oe2/gclk2 40 2 input/gclr 39 1 input/oe1 38 44 input/gclk1 37 43 i/o / gclk3 35 41 i/o / pd (1,2) 5, 19 11, 25 i/o / tdi (jtag) 1 7 i/o / tms (jtag) 7 13 i/o / tck (jtag) 26 32 i/o / tdo (jtag) 32 38 gnd 4, 16, 24, 36 10, 22, 30, 42 v cci 9, 17, 29, 41 3, 15, 23, 35 # of signal pins 36 36 # user i/o pins 32 32
atf1502asv(l) 15 atf1502asv i/o pinouts mc plc 44-lead plcc 44-lead tqfp 1a442 2a543 3a/ pd1 641 4a71 5a82 6a93 7a115 8/ tdi a126 9a137 10 a 14 8 11 a 16 10 12 a 17 11 13 a 18 12 14 a 19 13 15 a 20 14 16 a 21 15 17 b 41 35 18 b 40 34 19 b 39 33 20 b 38 32 21 b 37 31 22 b 36 30 23 b 34 28 24 b 33 27 25 b 32 26 26 b 31 25 27 b 29 23 28 b 28 22 29 b 27 21 30 b 26 20 31 b 25 19 32/ tms b2418
atf1502asv(l) 16 using ? c ? product for industrial there is very little risk in using ? c ? devices for industrial applications because the v cc conditions for 3.3v products are the same for commercial and industrial (there is only 15 c difference at the high end of the temperature range). to use commercial product for industrial temperature ranges, de-rate i cc by 15%. ordering information t pd (ns) t co1 (ns) f max (mhz) ordering code package operation range 15 8 100 atf1502asv-15 ac44 atf1502asv-15 jc44 44a 44j commercial (0 c to 70 c) 15 8 100 atf1502asv-15 ai44 atf1502asv-15 ji44 44a 44j industrial (-40 c to +85 c) 5 13 83.3 ATF1502ASVL-25 ac44 ATF1502ASVL-25 jc44 44a 44j commercial (0 c to 70 c) 5 13 83.3 ATF1502ASVL-25 ai44 ATF1502ASVL-25 ji44 44a 44j industrial (-40 c to +85 c) package type 44a 44-lead, thin plastic gull wing quad flatpack (tqfp) 44j 44-lead, plastic j-leaded chip carrier otp (plcc)
atf1502asv(l) 17 packaging information * controlling dimension: millimeters 1.20(0.047) max 10.10(0.394) 9.90(0.386) sq 12.21(0.478) 11.75(0.458) sq 0.75(0.030) 0.45(0.018) 0.15(0.006) 0.05(0.002) 0.20(.008) 0.09(.003) 0 7 0.80(0.031) bsc pin 1 id 0.45(0.018) 0.30(0.012) .045(1.14) x 45 pin no. 1 identify .045(1.14) x 30 - 45 .012(.305) .008(.203) .021(.533) .013(.330) .630(16.0) .590(15.0) .043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19) .500(12.7) ref sq .032(.813) .026(.660) .050(1.27) typ .022(.559) x 45 max (3x) .656(16.7) .650(16.5) .695(17.7) .685(17.4) sq sq 44a , 44-lead, thin (1.0 mm) plastic gull wing quad flat package (tqfp) dimensions in millimeters and (inches)* 44j , 44-lead, plastic j-leaded chip carrier (plcc) dimensions in inches and (millimeters) jedec standard ms-018 ac
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